Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
The increasing variability of process parameters leads to substantial parametric yield losses due to timing and leakage power constraints. Leakage power is especially affected by ...
Ashish Kumar Singh, Murari Mani, Michael Orshansky
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...