31 search results - page 4 / 7 » LimitLESS Directories: A Scalable Cache Coherence Scheme |
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
100
Voted
CDES
2008
14 years 11 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
88
Voted
SPAA
1998
ACM
15 years 2 months ago
1998
ACM
Modern shared-memory multiprocessors use complex memory system implementations that include a variety of non-trivial and interacting optimizations. More time is spent in verifying...
81
Voted
IEEEPACT
2003
IEEE
15 years 3 months ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...