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INFOCOM
2002
IEEE
15 years 5 months ago
Maintaining Packet Order In Two-stage Switches
-- High performance packet switches frequently use a centralized scheduler (also known as an arbiter) to determine the configuration of a non-blocking crossbar. The scheduler often...
Isaac Keslassy, Nick McKeown
107
Voted
ECRTS
1998
IEEE
15 years 4 months ago
Using exact feasibility tests for allocating real-time tasks in multiprocessor systems
This paper introduces improvements in partitioning schemes for multiprocessor real-time systems which allow higher processor utilization and enhanced schedulability by using exact...
Sergio Saez, Joan Vila i Carbó, Alfons Cres...
95
Voted
RTSS
1996
IEEE
15 years 4 months ago
Visual assessment of a real-time system design: a case study on a CNC controller
In this paper we describe our experiments on a realtime system design, focusing on design alternatives such as scheduling jitter, sensor-to-output latency, intertask communication...
Namyun Kim, Minsoo Ryu, Seongsoo Hong, Manas Sakse...
104
Voted
ANCS
2007
ACM
15 years 4 months ago
Congestion management for non-blocking clos networks
We propose a distributed congestion management scheme for non-blocking, 3-stage Clos networks, comprising plain buffered crossbar switches. VOQ requests are routed using multipath...
Nikolaos Chrysos
ICS
2000
Tsinghua U.
15 years 4 months ago
Hardware-only stream prefetching and dynamic access ordering
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
Chengqiang Zhang, Sally A. McKee