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» Limits of Work-Stealing Scheduling
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129
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PLDI
2003
ACM
15 years 3 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
76
Voted
ASAP
1997
IEEE
107views Hardware» more  ASAP 1997»
15 years 1 months ago
Tiling with limited resources
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to ...
Pierre-Yves Calland, Jack Dongarra, Yves Robert
65
Voted
FCCM
2000
IEEE
105views VLSI» more  FCCM 2000»
15 years 2 months ago
A Communication Scheduling Algorithm for Multi-FPGA Systems
For multiple FPGA systems, the limited number of I/O pins causes many problems. To solve these problems, efficient communication scheduling among FPGAs is crucial for obtaining hi...
Jinwoo Suh, Dong-In Kang, Stephen P. Crago
94
Voted
IJPP
2008
148views more  IJPP 2008»
14 years 10 months ago
Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems
We present an approach to the analysis and optimisation of heterogeneous multiprocessor embedded systems. The systems are heterogeneous not only in terms of hardware components, b...
Traian Pop, Paul Pop, Petru Eles, Zebo Peng
100
Voted
TCSV
2010
14 years 5 months ago
Cross-Layer Packet Retry Limit Adaptation for Video Transport Over Wireless LANs
Video transport over wireless networks requires retransmissions to successfully deliver video data to a receiver in case of packet loss, leading to increased delay time for the dat...
Chih-Ming Chen, Chia-Wen Lin, Yung-Chang Chen