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DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 2 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
CLOUD
2010
ACM
15 years 2 months ago
Comet: batched stream processing for data intensive distributed computing
Batched stream processing is a new distributed data processing paradigm that models recurring batch computations on incrementally bulk-appended data streams. The model is inspired...
Bingsheng He, Mao Yang, Zhenyu Guo, Rishan Chen, B...
ICPPW
2002
IEEE
15 years 2 months ago
Data Distribution Schemes of Sparse Arrays on Distributed Memory Multicomputers
A data distribution scheme of sparse arrays on a distributed memory multicomputer, in general, is composed of three phases, data partition, data distribution, and data compression...
Chun-Yuan Lin, Yeh-Ching Chung, Jen-Shiuh Liu
LPNMR
2001
Springer
15 years 1 months ago
plp: A Generic Compiler for Ordered Logic Programs
Abstract This paper describes a generic compiler, called plp, for translating ordered logic programs into standard logic programs under the answer set semantics. In an ordered logi...
James P. Delgrande, Torsten Schaub, Hans Tompits
EUROPAR
1999
Springer
15 years 1 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...