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ESA
2008
Springer
130views Algorithms» more  ESA 2008»
14 years 11 months ago
Linear Time Planarity Testing and Embedding of Strongly Connected Cyclic Level Graphs
Abstract. A level graph is a directed acyclic graph with a level assignment for each node. Such graphs play a prominent role in graph drawing. They express strict dependencies and ...
Christian Bachmaier, Wolfgang Brunner
GD
2003
Springer
15 years 3 months ago
Radial Level Planarity Testing and Embedding in Linear Time
A graph with an ordered k-partition of the vertices is radial level planar if there is a strictly outward drawing on k concentric levels without crossings. Radial level planarity ...
Christian Bachmaier, Franz-Josef Brandenburg, Mich...
ATS
2009
IEEE
162views Hardware» more  ATS 2009»
15 years 4 months ago
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients
—A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit...
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
DFT
2005
IEEE
109views VLSI» more  DFT 2005»
15 years 3 months ago
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
In Suk Chong, Antonio Ortega
ICCD
2002
IEEE
122views Hardware» more  ICCD 2002»
15 years 2 months ago
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits
Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for the automatic desi...
Sule Ozev, Alex Orailoglu