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LCTRTS
2001
Springer
15 years 7 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
ASPDAC
1999
ACM
107views Hardware» more  ASPDAC 1999»
15 years 7 months ago
New Multilevel and Hierarchical Algorithms for Layout Density Control
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Alex...
112
Voted
DAC
1999
ACM
15 years 7 months ago
On ILP Formulations for Built-In Self-Testable Data Path Synthesis
In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, ...
Han Bin Kim, Dong Sam Ha, Takeshi Takahashi
143
Voted
DATE
1999
IEEE
127views Hardware» more  DATE 1999»
15 years 7 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
ICCAD
1999
IEEE
66views Hardware» more  ICCAD 1999»
15 years 7 months ago
Test scheduling for core-based systems
We present optimal solutions to the test scheduling problem for core-based systems. We show that test scheduling is equivalent to the m-processor open-shop scheduling problem and ...
Krishnendu Chakrabarty