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ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
15 years 11 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
117
Voted
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
15 years 11 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
130
Voted
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
15 years 11 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
112
Voted
CVPR
2010
IEEE
15 years 10 months ago
Efficiently Selecting Regions for Scene Understanding
Recent advances in scene understanding and related tasks have highlighted the importance of using regions to reason about high-level scene structure. Typically, the regions are ...
M. Pawan Kumar, Daphne Koller
ISPD
2010
ACM
177views Hardware» more  ISPD 2010»
15 years 9 months ago
Skew management of NBTI impacted gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant failure mechanism for PMOS in nanometer IC designs. However, its impact on one of the most important compo...
Ashutosh Chakraborty, David Z. Pan