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DAC
2009
ACM
15 years 4 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
HIPEAC
2009
Springer
15 years 4 months ago
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semico...
Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Pa...
ICSE
2009
IEEE-ACM
15 years 4 months ago
MINTS: A general framework and tool for supporting test-suite minimization
Regression test suites tend to grow over time as new test cases are added to exercise new functionality or to target newly-discovered faults. When test suites become too large, th...
Hwa-You Hsu, Alessandro Orso
CSFW
2009
IEEE
15 years 4 months ago
More Anonymous Onion Routing Through Trust
We consider using trust information to improve the anonymity provided by onion-routing networks. In particular, we introduce a model of trust in network nodes and use it to design...
Aaron Johnson, Paul F. Syverson
91
Voted
FOCS
2009
IEEE
15 years 4 months ago
Reducibility among Fractional Stability Problems
— In a landmark paper [32], Papadimitriou introduced a number of syntactic subclasses of TFNP based on proof styles that (unlike TFNP) admit complete problems. A recent series of...
Shiva Kintali, Laura J. Poplawski, Rajmohan Rajara...