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» Linear decomposition algorithm for VLSI design applications
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GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 10 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
143
Voted
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
15 years 7 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
156
Voted
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
15 years 9 months ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...
GLVLSI
2009
IEEE
131views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Octilinear redistributive routing in bump arrays
This paper proposes a scheme for automatic re-distribution layer (RDL) routing, which is used in chip-package connections. Traditional RDL routing designs are mostly performed man...
Renshen Wang, Chung-Kuan Cheng
149
Voted
SAC
2003
ACM
15 years 9 months ago
ARCHITECT-R: A System for Reconfigurable Robots Design
An increasing interest in the design of mobile robots has been observed in recent years, which is mainly motivated by technological advances that may allow their application to co...
R. A. Gonçalves, P. A. Moraes, João ...