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» Linear decomposition algorithm for VLSI design applications
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VLSID
2007
IEEE
153views VLSI» more  VLSID 2007»
16 years 2 months ago
Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
Zhaohui Fu, Sharad Malik
FCCM
2007
IEEE
134views VLSI» more  FCCM 2007»
15 years 8 months ago
FPGA-accelerated seed generation in Mercury BLASTP
BLASTP is the most popular tool to perform comparative sequence analysis of protein sequences. An exponential increase in the size of protein sequence databases in recent years, h...
Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhle...
IPPS
1998
IEEE
15 years 6 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani
JCO
1998
136views more  JCO 1998»
15 years 1 months ago
A Greedy Randomized Adaptive Search Procedure for the Feedback Vertex Set Problem
Abstract. A Greedy Randomized Adaptive Search Procedure (GRASP) is a randomized heuristic that has produced high quality solutions for a wide range of combinatorial optimization pr...
Panos M. Pardalos, Tianbing Qian, Mauricio G. C. R...
VLSID
2002
IEEE
128views VLSI» more  VLSID 2002»
16 years 2 months ago
System-Level Point-to-Point Communication Synthesis using Floorplanning Information
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...
Jingcao Hu, Yangdong Deng, Radu Marculescu