318 search results - page 62 / 64 » Link-Level Network Topology Generation |
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
ACSC
2003
IEEE
15 years 2 months ago
2003
IEEE
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
NGC
2000
Springer
15 years 1 months ago
2000
Springer
Several architectures have been recently proposed to support IP mobility. Most studies, however, show that current protocols, in general, fall short from satisfying the performanc...
102
Voted
ISPD
2004
ACM
15 years 2 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
85
Voted
GECCO
2010
Springer
15 years 2 months ago
2010
Springer
The Hypercube-based NeuroEvolution of Augmenting Topologies (HyperNEAT) approach demonstrated that the pattern of weights across the connectivity of an artificial neural network ...