This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits effic...
Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. My...
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...
This paper proposes a new approach for the hazard checking of timed asynchronous circuits. Previous papers proposed either exact algorithms, which suffer from statespace explosion...
In the recent years, there have been a large amount of investigations on safety verification of uncertain continuous systems. In engineering and applied mathematics, this verificat...
Ensuring correctness of software by formal methods is a very relevant and widely studied problem. Automatic verification of software using model checkers from the state space exp...