Abstract. Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptio...
Abstract. Multithreaded programs are prone to errors caused by unintended interference between concurrent threads. This paper focuses on verifying that deterministically-parallel c...
Caitlin Sadowski, Stephen N. Freund, Cormac Flanag...
d Abstract) Vijay Saraswat1 and Radha Jagadeesan2 1 IBM T.J. Watson Research Lab 2 School of CTI, DePaul University Abstract. We present the concurrency and distribution primitives...
There are few published examples of the proof of correctness of a cache-coherence protocol expressed in an HDL. A designer generally shows the correctness of a protocol ny impleme...
We present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee)...