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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 10 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ICCAD
1997
IEEE
112views Hardware» more  ICCAD 1997»
15 years 10 months ago
Circuit optimization via adjoint Lagrangians
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
IWANN
1997
Springer
15 years 10 months ago
The Pattern Extraction Architecture: A Connectionist Alternative to the Von Neumann Architecture
A detailed connectionist architecture is described which is capable of relating psychological behavior to the functioning of neurons and neurochemicals. The need to be able to bui...
L. Andrew Coward
SIGMOD
1993
ACM
163views Database» more  SIGMOD 1993»
15 years 10 months ago
The LRU-K Page Replacement Algorithm For Database Disk Buffering
This paper introduces a new approach to database disk buffering, called the LRU–K method. The basic idea of LRU–K is to keep track of the times of the last K references to pop...
Elizabeth J. O'Neil, Patrick E. O'Neil, Gerhard We...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Node Mergers in the Presence of Don't Cares
Abstract-- SAT sweeping is the process of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent all the other equivalent nodes. This ...
Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Vale...