1929 search results - page 117 / 386 » Load Balancing with Memory |
121
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MICRO
1998
IEEE
15 years 7 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
132
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CORR
2010
Springer
15 years 19 days ago
2010
Springer
We consider the discrepancy problem of coloring n intervals with k colors such that at each point on the line, the maximal difference between the number of intervals of any two co...
115
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INFOCOM
2008
IEEE
15 years 9 months ago
2008
IEEE
— Due to the increased usage of NAT boxes and firewalls, it has become harder for applications to establish direct connections seamlessly among two end-hosts. A recently adopted...
133
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ISCA
2005
IEEE
15 years 8 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
289
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ICDE
2005
IEEE
16 years 4 months ago
2005
IEEE
We study several transparent techniques for scaling dynamic content web sites, and we evaluate their relative impact when used in combination. Full transparency implies strong dat...