Sciweavers

1929 search results - page 150 / 386
» Load Balancing with Memory
Sort
View
104
Voted
ASPLOS
2010
ACM
15 years 7 months ago
Flexible architectural support for fine-grain scheduling
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis
109
Voted
DAMON
2009
Springer
15 years 7 months ago
Cache-conscious buffering for database operators with state
Database processes must be cache-efficient to effectively utilize modern hardware. In this paper, we analyze the importance of temporal locality and the resultant cache behavior ...
John Cieslewicz, William Mee, Kenneth A. Ross
118
Voted
IPPS
2006
IEEE
15 years 6 months ago
An extensible global address space framework with decoupled task and data abstractions
ions Sriram Krishnamoorthy½ Umit Catalyurek¾ Jarek Nieplocha¿ Atanas Rountev½ P. Sadayappan½ ½ Dept. of Computer Science and Engineering, ¾ Dept. of Biomedical Informatics T...
Sriram Krishnamoorthy, Ümit V. Çataly&...
PADS
2003
ACM
15 years 6 months ago
HLA-based Adaptive Distributed Simulation of Wireless Mobile Systems
Wireless networks’ models differ from wired ones at least in the innovative dynamic effects of host-mobility and open-broadcast nature of the wireless medium. Topology changes d...
Luciano Bononi, Gabriele D'Angelo, Lorenzo Donatie...
149
Voted
RTAS
1997
IEEE
15 years 5 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford