1929 search results - page 166 / 386 » Load Balancing with Memory |
84
Voted
ASPDAC
2009
ACM
15 years 5 months ago
2009
ACM
—Multi-core microarchitectures require a careful balance between many competing objectives to achieve the highest possible performance. Integrated Early Analysis is the considera...
90
Voted
ISCA
2007
IEEE
15 years 7 months ago
2007
IEEE
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
118
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CSCW
2012
ACM
13 years 8 months ago
2012
ACM
Meeting participants can experience cognitive overload when they need both to verbally contribute to ongoing discussion while simultaneously creating notes to promote later recall...
113
Voted
ANCS
2009
ACM
14 years 10 months ago
2009
ACM
Ubiquitous multi-core-based web servers and edge routers are increasingly popular in deploying computationally intensive Deep Packet Inspection (DPI) programs. Previous work has s...
107
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ISCA
2005
IEEE
15 years 6 months ago
2005
IEEE
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...