Sciweavers

1929 search results - page 189 / 386
» Load Balancing with Memory
Sort
View
112
Voted
PC
2007
173views Management» more  PC 2007»
15 years 6 days ago
Parallel graphics and visualization
Parallel volume rendering is one of the most efficient techniques to achieve real time visualization of large datasets by distributing the data and the rendering process over a c...
Luís Paulo Santos, Bruno Raffin, Alan Heiri...
113
Voted
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 5 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
124
Voted
ASPLOS
1987
ACM
15 years 4 months ago
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures
This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting...
Richard F. Rashid, Avadis Tevanian, Michael Young,...
70
Voted
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
15 years 5 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
163
Voted
DSN
2011
IEEE
14 years 15 days ago
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
Phase change memory (PCM) has emerged as a promising technology for main memory due to many advan­ tages, such as better scalability, non-volatility and fast read access. However,...
Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers,...