1929 search results - page 190 / 386 » Load Balancing with Memory |
123
Voted
ICS
2005
Tsinghua U.
15 years 6 months ago
2005
Tsinghua U.
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
124
Voted
VLDB
1999
ACM
15 years 5 months ago
1999
ACM
As random access memory gets cheaper, it becomes increasingly affordable to build computers with large main memories. We consider decision support workloads within the context of...
110
Voted
ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
106
Voted
ISCA
2009
IEEE
15 years 7 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
112
Voted
CHI
2004
ACM
15 years 6 months ago
2004
ACM
We introduce Topobo, a 3D constructive assembly system embedded with kinetic memory, the ability to record and playback physical motion. Unique among modeling systems is Topoboʼs...