141 search results - page 3 / 29 » Load Execution Latency Reduction |
ICS
2004
Tsinghua U.
13 years 11 months ago
2004
Tsinghua U.
In contemporary out-of-order superscalar design, high IPC is mainly achieved by exposing high instruction level parallelism (ILP). Scaling issue window size can certainly provide ...
ISCA
1999
IEEE
13 years 10 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
ASPLOS
1998
ACM
13 years 10 months ago
1998
ACM
In order to execute a program on a remote computer, it must first be transferred over a network. This transmission incurs the overhead of network latency before execution can beg...
JSA
2010
13 years 4 months ago
2010
— Effective address calculation for load and store instructions needs to compete for ALU with other instructions and hence extra latencies might be incurred to data cache accesse...
IISWC
2006
IEEE
14 years 10 days ago
2006
IEEE
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...