141 search results - page 7 / 29 » Load Execution Latency Reduction |
174
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HPCA
2008
IEEE
16 years 5 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
143
Voted
IPPS
2003
IEEE
15 years 10 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
170
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DAC
2005
ACM
16 years 6 months ago
2005
ACM
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
155
Voted
MICRO
2005
IEEE
15 years 10 months ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
149
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EMSOFT
2009
Springer
15 years 11 months ago
2009
Springer
Scratchpads have been widely proposed as an alternative to caches for embedded systems. Advantages of scratchpads include reduced energy consumption in comparison to a cache and a...