141 search results - page 8 / 29 » Load Execution Latency Reduction |
HPCA
1998
IEEE
15 years 3 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
IPPS
2009
IEEE
15 years 6 months ago
2009
IEEE
Power consumption is a very important issue for HPC community, both at the level of one application or at the level of whole workload. Load imbalance of a MPI application can be e...
HPCA
2005
IEEE
16 years 14 hour ago
2005
IEEE
This paper introduces a novel technique which leverages value prediction and multithreading on a simultaneous multithreading processor to achieve higher performance in a single th...
111
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ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
120
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HPCA
2000
IEEE
15 years 4 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...