162 search results - page 10 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
122
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DSD
2011
IEEE
13 years 9 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
101
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ICDCS
1995
IEEE
15 years 1 months ago
1995
IEEE
One of the mostsoughtaftersoftware innovation of thisdecade is the construction of systems using off-the-shelf workstations that actually deliver, and even surpass, the power and ...
CORR
2008
Springer
14 years 9 months ago
2008
Springer
In this paper, we describe a proactive recovery scheme based on service migration for long-running Byzantine fault tolerant systems. Proactive recovery is an essential method for ...
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Runtime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...