162 search results - page 12 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
83
Voted
ISCAPDCS
2004
14 years 11 months ago
2004
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
102
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DAC
2005
ACM
15 years 10 months ago
2005
ACM
Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
122
Voted
BSDCON
2003
14 years 11 months ago
2003
The existing thread scheduler in FreeBSD was well suited towards the computing environment that it was developed in. As the priorities and hardware targets of the project have cha...
ICS
1999
Tsinghua U.
15 years 1 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...