162 search results - page 15 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
HPCA
2004
IEEE
15 years 10 months ago
2004
IEEE
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
ICMCS
2007
IEEE
15 years 3 months ago
2007
IEEE
The H.264 decoder has a sequential, control intensive front end that makes it difficult to leverage the potential performance of emerging manycore processors. Preparsing is a fun...
EUROPAR
2005
Springer
15 years 3 months ago
2005
Springer
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
ICS
2001
Tsinghua U.
15 years 2 months ago
2001
Tsinghua U.
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
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INFOCOM
2009
IEEE
15 years 4 months ago
2009
IEEE
—Energy use of computer communication systems has quickly become a vital design consideration. One effective method for reducing energy consumption is dynamic speed scaling, whic...