162 search results - page 16 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
HPCA
2004
IEEE
15 years 10 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
SC
1995
ACM
15 years 1 months ago
1995
ACM
We describe the design of a runtime system for a fine-grained concurrent object-oriented (actor) language and its performance. The runtime system provides considerable flexibility...
CLUSTER
2001
IEEE
15 years 1 months ago
2001
IEEE
Using multiple independent networks (also known as rails) is an emerging technique to overcome bandwidth limitations and enhance fault tolerance of current high-performance parall...
145
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VLDB
2007
ACM
15 years 9 months ago
2007
ACM
This paper analyzes the performance of concurrent (index) scan operations in both record (NSM/PAX) and column (DSM) disk storage models and shows that existing scheduling policies...
104
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ICS
2007
Tsinghua U.
15 years 3 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...