162 search results - page 17 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
78
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
MICRO
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...