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» Load Latency Tolerance in Dynamically Scheduled Processors
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CASES
2009
ACM
15 years 4 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
CF
2010
ACM
15 years 2 months ago
EXACT: explicit dynamic-branch prediction with active updates
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a...
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg
74
Voted
PPL
2006
81views more  PPL 2006»
14 years 9 months ago
Microthreading a Model for Distributed Instruction-level Concurrency
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
Chris R. Jesshope
LCN
2002
IEEE
15 years 2 months ago
A Locally Coordinated Scatternet Scheduling Algorithm
There is growing interest in wireless personal area networks built from portable devices equipped with shortrange radio interfaces such as Bluetooth. These small networks (called ...
Godfrey Tan, John V. Guttag
CASES
2006
ACM
15 years 1 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...