162 search results - page 22 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
92
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ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to transient faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR...
IEEEPACT
1999
IEEE
15 years 1 months ago
1999
IEEE
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...
122
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NOSSDAV
1992
Springer
15 years 1 months ago
1992
Springer
: We present an overview of a "best-effort" transport protocol that supports conferencing with digital audio and video across interconnected packet switched networks. The...
CEE
2007
14 years 9 months ago
2007
Real-time systems are often designed using preemptive scheduling and worst-case execution time estimates to guarantee the execution of high priority tasks. There is, however, an i...
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...