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» Load Latency Tolerance in Dynamically Scheduled Processors
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ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 2 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
15 years 2 months ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
SOSP
1989
ACM
14 years 10 months ago
Process Control and Scheduling Issues for Multiprogrammed Shared-Memory Multiprocessors
Shared-memory multiprocessors are frequently used in a timesharing style with multiple parallel applications executing at the same time. In such an environment, where the machine ...
Andrew Tucker, Anoop Gupta
89
Voted
IPPS
2003
IEEE
15 years 2 months ago
The Case for Fair Multiprocessor Scheduling
Partitioning and global scheduling are two approaches for scheduling real-time tasks on multiprocessors. Though partitioning is sub-optimal, it has traditionally been preferred; t...
Anand Srinivasan, Philip Holman, James H. Anderson...
PC
2011
413views Management» more  PC 2011»
14 years 4 months ago
Exploiting thread-level parallelism in the iterative solution of sparse linear systems
We investigate the efficient iterative solution of large-scale sparse linear systems on shared-memory multiprocessors. Our parallel approach is based on a multilevel ILU precondit...
José Ignacio Aliaga, Matthias Bollhöfe...