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» Load Latency Tolerance in Dynamically Scheduled Processors
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MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
14 years 9 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
JIPS
2006
126views more  JIPS 2006»
14 years 9 months ago
TASL: A Traffic-Adapted Sleep/Listening MAC Protocol for Wireless Sensor Network
In this paper, we proposed a MAC protocol, which can dynamically adjust Listening/Sleeping time rate of wireless sensor nodes according to data traffic load. In sensor networks, se...
Yuan Yang, Zhen Fu, Tae-Seok Lee, Myong-Soon Park
CASES
2009
ACM
15 years 4 months ago
Towards scalable reliability frameworks for error prone CMPs
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
Joseph Sloan, Rakesh Kumar
EMSOFT
2008
Springer
14 years 11 months ago
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications
In this paper, we propose a generalized clustering approach for static data flow subgraphs mapped onto individual processors in Multi-Processor System on Chips (MPSoCs). The goal ...
Joachim Falk, Joachim Keinert, Christian Haubelt, ...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 10 months ago
Power-aware Multimedia Systems using Run-time Prediction
The need for low-power multimedia processing is integral to portable and embedded devices such as cell phones, wireless terminals, multimedia handhelds and PDAs. The multimedia pr...
Pavan Kumar, Mani B. Srivastava