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» Load Latency Tolerance in Dynamically Scheduled Processors
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ICPP
1998
IEEE
15 years 1 months ago
A memory-layout oriented run-time technique for locality optimization
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
Yong Yan, Xiaodong Zhang, Zhao Zhang
SENSYS
2003
ACM
15 years 2 months ago
Practical lazy scheduling in sensor networks
Experience has shown that the power consumption of sensors and other wireless computational devices is often dominated by their communication patterns. We present a practical real...
Ramana Rao Kompella, Alex C. Snoeren
SC
1995
ACM
15 years 1 months ago
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
Umakishore Ramachandran, Gautam Shah, Anand Sivasu...
ICPP
2009
IEEE
15 years 4 months ago
Code Semantic-Aware Runahead Threads
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
Tanausú Ramírez, Alex Pajuelo, Olive...
84
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SC
2004
ACM
15 years 3 months ago
Performance Evaluation of Task Pools Based on Hardware Synchronization
A task-based execution provides a universal approach to dynamic load balancing for irregular applications. Tasks are arbitrary units of work that are created dynamically at runtim...
Ralf Hoffmann, Matthias Korch, Thomas Rauber