162 search results - page 27 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
102
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MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
HIPC
2005
Springer
15 years 3 months ago
2005
Springer
We recently proposed a new approach to parallelization, by decomposing the time domain, instead of the conventional space domain. This improves latency tolerance, and we demonstrat...
HPCA
2012
IEEE
13 years 5 months ago
2012
IEEE
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
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LCTRTS
2000
Springer
15 years 1 months ago
2000
Springer
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...