162 search results - page 5 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
EUROPAR
2001
Springer
15 years 2 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
113
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PRDC
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents the performance analysis of several well-known partitioning scheduling algorithms in real-time and fault-tolerant multiprocessor systems. Both static and dynam...
102
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CGO
2006
IEEE
15 years 3 months ago
2006
IEEE
Software prefetching has been demonstrated as a powerful technique to tolerate long load latencies. However, to be effective, prefetching must target the most critical (frequently...
PLDI
1995
ACM
15 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
104
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PDP
2008
IEEE
15 years 4 months ago
2008
IEEE
Search engines use inverted files as index data structures to speed up the solution of user queries. The index is distributed on a set of processors forming a cluster of computer...