162 search results - page 9 / 33 » Load Latency Tolerance in Dynamically Scheduled Processors |
103
Voted
PPOPP
2009
ACM
15 years 10 months ago
2009
ACM
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
LCTRTS
2004
Springer
15 years 3 months ago
2004
Springer
This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches ...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
NOCS
2007
IEEE
15 years 3 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...