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» Load-Reuse Analysis: Design and Evaluation
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TC
2008
14 years 10 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
BCB
2010
138views Bioinformatics» more  BCB 2010»
14 years 5 months ago
Comparative analysis of biclustering algorithms
Biclustering is a very popular method to identify hidden co-regulation patterns among genes. There are numerous biclustering algorithms designed to undertake this challenging task...
Doruk Bozdag, Ashwin S. Kumar, Ümit V. &Ccedi...
IPPS
1999
IEEE
15 years 2 months ago
A Factorial Performance Evaluation for Hierarchical Memory Systems
In this study, we introduce an evaluation methodology for advanced memory systems. This methodology is based on statistical factorial analysis. It is two fold: it first determines...
Xian-He Sun, Dongmei He, Kirk W. Cameron, Yong Luo
GLVLSI
2007
IEEE
107views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Side-channel resistant system-level design flow for public-key cryptography
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingr...
GLOBAL
2003
Springer
15 years 3 months ago
Performance Evaluation for Global Computation
Abstract. Global computing applications co-ordinate distributed computations across widely-dispersed hosts. Such systems present formidable design and implementation challenges to ...
Linda Brodo, Pierpaolo Degano, Stephen Gilmore, Ja...