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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 3 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
CSB
2005
IEEE
152views Bioinformatics» more  CSB 2005»
15 years 3 months ago
Consensus Genetic Maps: A Graph Theoretic Approach
A genetic map is an ordering of genetic markers constructed from genetic linkage data for use in linkage studies and experimental design. While traditional methods have focused on...
Benjamin G. Jackson, Srinivas Aluru, Patrick S. Sc...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 3 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
IEEESCC
2005
IEEE
15 years 3 months ago
Web Services Composition: A Story of Models, Automata, and Logics
eal world”, represented abstractly using (time-varying) first-order logic predicates and terms. A representative composition result [11] here uses a translation into Petri nets. ...
Richard Hull
66
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ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
15 years 3 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang