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90
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DAC
2012
ACM
13 years 3 months ago
Improving gate-level simulation accuracy when unknowns exist
Unknown values (Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be hand...
Kai-Hui Chang, Chris Browy
118
Voted
ARTS
1999
Springer
15 years 5 months ago
Quantitative Program Logic and Performance in Probabilistic Distributed Algorithms
In this paper we show how quantitative program logic [14] provides a formal framework in which to promote standard techniques of program analysis to a context where probability and...
Annabelle McIver
106
Voted
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
15 years 9 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
EH
2003
IEEE
127views Hardware» more  EH 2003»
15 years 6 months ago
Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits
In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and ...
Carlos A. Coello Coello, Enrique Alba, Gabriel Luq...
FOCS
1989
IEEE
15 years 4 months ago
A Really Temporal Logic
We introduce a temporal logic for the speci cation of real-time systems. Our logic, TPTL, employs a novel quanti er construct for referencing time: the freeze quanti er binds a var...
Rajeev Alur, Thomas A. Henzinger