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IESS
2007
Springer
120views Hardware» more  IESS 2007»
16 years 14 days ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
LCTRTS
2007
Springer
16 years 14 days ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski
IISWC
2006
IEEE
16 years 10 days ago
Performance Analysis of Sequence Alignment Applications
— Recent advances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a m...
Friman Sánchez, Esther Salamí, Alex ...
SCESM
2006
ACM
238views Algorithms» more  SCESM 2006»
16 years 8 days ago
Nobody's perfect: interactive synthesis from parametrized real-time scenarios
As technical systems keep growing more complex and sophisticated, designing software for the safety-critical coordination between their components becomes increasingly difficult....
Holger Giese, Stefan Henkler, Martin Hirsch, Flori...
ISLPED
2005
ACM
109views Hardware» more  ISLPED 2005»
15 years 12 months ago
Power reduction by varying sampling rate
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...
William R. Dieter, Srabosti Datta, Wong Key Kai