—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
—Knowing accurate positions of nodes in wireless ad-hoc and sensor networks is essential for a wide range of pervasive and mobile applications. However, errors are inevitable in ...
In this paper we propose a new parallelization scheme for Simulated Annealing — Hierarchical Parallel SA (HPSA). This new scheme features coarse-granularity in parallelization, d...
Shiming Xu, Wenguang Chen, Weimin Zheng, Tao Wang,...
We consider the class of database programs and address the problem of minimizing the cost of their exchanges with the database server. This cost partly consists of query execution...
Abstract—In two recent contributions [1], [2], we have provided a comparative analysis of various optimization algorithms, which can be used for atomic location estimation, and s...
Stefano Tennina, Marco Di Renzo, Fabio Graziosi, F...