In the design of highly complex, heterogeneous, and concurrent systems, deadlock detection and resolution remains an important issue. In this paper, we systematically analyze the ...
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. S...
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...