202 search results - page 11 / 41 » Location cache: a low-power L2 cache system |
85
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ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
HPCA
2001
IEEE
16 years 3 days ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
112
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CASES
2008
ACM
15 years 1 months ago
2008
ACM
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
HIPEAC
2007
Springer
15 years 5 months ago
2007
Springer
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
120
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IISWC
2008
IEEE
15 years 6 months ago
2008
IEEE
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...