202 search results - page 13 / 41 » Location cache: a low-power L2 cache system |
114
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ADHOC
2007
14 years 12 months ago
2007
Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congest...
101
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IEEEPACT
2005
IEEE
15 years 5 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
102
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IPCCC
2006
IEEE
15 years 5 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
ISCA
1998
IEEE
15 years 4 months ago
1998
IEEE
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...