202 search results - page 20 / 41 » Location cache: a low-power L2 cache system |
105
click to vote
CC
2008
Springer
15 years 1 months ago
2008
Springer
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
CODES
2000
IEEE
15 years 4 months ago
2000
IEEE
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...
108
click to vote
CCGRID
2008
IEEE
15 years 6 months ago
2008
IEEE
The advances in multicore technology and modern interconnects is rapidly accelerating the number of cores deployed in today’s commodity clusters. A majority of parallel applicat...
111
click to vote
NOCS
2007
IEEE
15 years 6 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...