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» Logic Programming and Model Checking
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DAC
2006
ACM
16 years 3 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
ATVA
2006
Springer
133views Hardware» more  ATVA 2006»
15 years 6 months ago
Branching-Time Property Preservation Between Real-Time Systems
In the past decades, many formal frameworks (e.g. timed automata and temporal logics) and techniques (e.g. model checking and theorem proving) have been proposed to model a real-ti...
Jinfeng Huang, Marc Geilen, Jeroen Voeten, Henk Co...
TACAS
2007
Springer
141views Algorithms» more  TACAS 2007»
15 years 8 months ago
JPF-SE: A Symbolic Execution Extension to Java PathFinder
We present JPF–SE, an extension to the Java PathFinder Model Checking framework (JPF) that enables the symbolic execution of Java programs. JPF–SE uses JPF to generate and expl...
Saswat Anand, Corina S. Pasareanu, Willem Visser
FDL
2004
IEEE
15 years 6 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
JUCS
2008
120views more  JUCS 2008»
15 years 2 months ago
An Adaptation Logic Framework for Java-based Component Systems
Abstract: This paper describes a Java-based framework for developing componentbased software systems supporting adaptation with logic laws and considering component interactions as...
Enrico Oliva, Antonio Natali, Alessandro Ricci, Mi...