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DATE
2006
IEEE
124views Hardware» more  DATE 2006»
15 years 3 months ago
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
LICS
2003
IEEE
15 years 2 months ago
Model checking for probability and time: from theory to practice
Probability features increasingly often in software and hardware systems: it is used in distributed co-ordination and routing problems, to model fault-tolerance and performance, a...
Marta Z. Kwiatkowska
ICALP
1998
Springer
15 years 1 months ago
Deciding Bisimulation-Like Equivalences with Finite-State Processes
We show that characteristic formulae for nite-state systems up to bisimulationlike equivalences (e.g., strong and weak bisimilarity) can be given in the simple branching-time temp...
Petr Jancar, Antonín Kucera, Richard Mayr
OOPSLA
2007
Springer
15 years 3 months ago
Modular typestate checking of aliased objects
Objects often define usage protocols that clients must follow in order for these objects to work properly. Aliasing makes it notoriously difficult to check whether clients and i...
Kevin Bierhoff, Jonathan Aldrich
CORR
2010
Springer
174views Education» more  CORR 2010»
14 years 6 months ago
A Proof Carrying Code Framework for Inlined Reference Monitors in Java Bytecode
We propose a lightweight approach for certification of Java bytecode monitor inlining using proof-carrying code. The main purpose of such a framework is to enable development use ...
Mads Dam, Andreas Lundblad