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» Logic Synthesis for Engineering Change
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ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
15 years 4 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
127
Voted
ICSE
1993
IEEE-ACM
15 years 4 months ago
"...And Nothing Else Changes": The Frame Problem in Procedure Specifications
We give examples of situations where formal specifications of procedures in the standard pre/postcondition style become lengthy, cumbersome and difficult to change, a problem whic...
Alexander Borgida, John Mylopoulos, Raymond Reiter
107
Voted
CODES
2001
IEEE
15 years 4 months ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
GECCO
2006
Springer
202views Optimization» more  GECCO 2006»
15 years 4 months ago
Human competitive security protocols synthesis
This poster paper outlines a method for a search based approach to the development of provably correct protocols. Categories and Subject Descriptors C.2.2 [Computer Communication ...
Hao Chen, John A. Clark, Jeremy Jacob
94
Voted
JAIR
2010
145views more  JAIR 2010»
14 years 11 months ago
On Action Theory Change
As historically acknowledged in the Reasoning about Actions and Change community, intuitiveness of a logical domain description cannot be fully automated. Moreover, like any other...
Ivan José Varzinczak