This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
We give examples of situations where formal specifications of procedures in the standard pre/postcondition style become lengthy, cumbersome and difficult to change, a problem whic...
Alexander Borgida, John Mylopoulos, Raymond Reiter
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
This poster paper outlines a method for a search based approach to the development of provably correct protocols. Categories and Subject Descriptors C.2.2 [Computer Communication ...
As historically acknowledged in the Reasoning about Actions and Change community, intuitiveness of a logical domain description cannot be fully automated. Moreover, like any other...