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» Logic Synthesis for Engineering Change
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ICCS
2007
Springer
15 years 1 months ago
Building Verifiable Sensing Applications Through Temporal Logic Specification
Abstract. Sensing is at the core of virtually every DDDAS application. Sensing applications typically involve distributed communication and coordination over large self-organized n...
Asad Awan, Ahmed H. Sameh, Suresh Jagannathan, Ana...
OOPSLA
2004
Springer
15 years 3 months ago
Chianti: a tool for change impact analysis of java programs
This paper reports on the design and implementation of Chianti, a change impact analysis tool for Java that is implemented in the context of the Eclipse environment. Chianti analy...
Xiaoxia Ren, Fenil Shah, Frank Tip, Barbara G. Ryd...
COMPSAC
2006
IEEE
15 years 3 months ago
Automated Agent Synthesis for Situation Awareness in Service-Based Systems
Service-based systems have many applications, such as collaborative research and development, e-business, health care, military applications, and homeland security. In dynamic ser...
Stephen S. Yau, Haishan Gong, Dazhi Huang, Wei Gao...
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DAC
2008
ACM
15 years 10 months ago
Type-matching clock tree for zero skew clock gating
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-...
EUROMICRO
2000
IEEE
15 years 2 months ago
Task Assignment and Scheduling under Memory Constraints
Many DSP and image processing embedded systems have hard memory constraints which makes it difficult to find a good task assignment and scheduling which fulfill these constrain...
Radoslaw Szymanek, Krzysztof Kuchcinski