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» Logic Synthesis for Engineering Change
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ITC
1999
IEEE
78views Hardware» more  ITC 1999»
15 years 1 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
ISORC
2009
IEEE
15 years 4 months ago
Component Based Middleware-Synthesis for AUTOSAR Basic Software
Distributed real-time automotive embedded systems have to be highly dependable as well as cost-efficient due to the large number of manufactured units. To close the gap between r...
Dietmar Schreiner, Markus Schordan, Karl M. Gö...
CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 2 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
JANCL
2007
106views more  JANCL 2007»
14 years 9 months ago
Dynamic logic for belief revision
ABSTRACT. We show how belief revision can be treated systematically in the format of dynamicepistemic logic, when operators of conditional belief are added. The core engine consist...
Johan van Benthem